Power-aware design-for-test: a survey of DFT techniques and scan chain reordering approaches

Abstract

The rapid scaling of semiconductor technologies has significantly increased the integration density and introduced new categories of manufacturing defects, thereby increasing the test complexity and time. Scan-based design for-test (DFT) architectures remain the most widely adopted method for digital IC testing, where test vectors are shifted serially into and out of scan chains. Because shift operations dominate the overall test time, reducing power during scan shifting is essential to prevent IR-drop, thermal issues, reliability degradation, and potential yield loss, and to enable higher shift frequencies. A higher shift frequency directly reduces the test application time and, consequently, the overall test cost. Excessive switching during scan shift remains a significant challenge, particularly in today’s low-power devices, prompting extensive research on low-power DFT. This paper presents a structured survey of recent advancements in shift-power reduction, covering automatic test pattern generation (ATPG)-based low power test pattern generation, built-in self-test (BIST)-based low-transition pattern generation, and modern scan-chain optimization and reordering strategies. The survey highlights that among various solutions, scan chain reordering stands out as one of the most effective and scalable power-aware DFT techniques, due to its minimal implementation overhead, seamless integration with existing ATPG/BIST flows, and significant ability to reduce 20–50% scan-shift power without requiring pattern regeneration.