Optimization of single electron transistor based digital logic design

Abstract

This paper addresses the challenge of high-power consumption and delay in conventional complementary metal-oxide-semiconductor (CMOS) circuits, particularly in the design of digital logic gates. The objective is to develop a hybrid CMOS-single-electron transistor (SET) model that reduces power consumption while maintaining acceptable performance in terms of delay. The proposed model leverages coulomb oscillation in SETs to create a changeable transconductance area, which significantly reduces energy usage. Simulation results demonstrates that the hybrid CMOS-SET circuits achieve up to 30% lower power dissipation compared to traditional CMOS designs, although a slight increase in delay is observed in complex gates like the OR gate. The novelty of this work lies in its use of coulomb oscillation for dynamic transconductance control, providing an innovative approach to balancing power efficiency and speed in nano-scale digital circuits. This makes the proposed model a promising candidate for future low-power, high-performance integrated circuits.