Three-Stage Amplifier Adopting Dual-Miller with Nulling-Resistor and Dual-Feedforward Techniques

Zhou Qianneng, Li Qi, Li Chen, Lin Jinzhao, Li Hongjuan, Li Yunsong, Pang Yu, Li Guoquan, Cai Xuemei

Abstract


A high-gain wide-bandwidth three-stage amplifier, which employs dual-miller compensation with nulling-resistor and dual-feedforward compensation (DMCNR-DFC), is designed and analyzed in this paper. By adopting the technique of DMCNR-DFC, the designed three-stage amplifier achieves well performance including gain-bandwidth product (GBW) and slew rate (SR). The improved DMCNR-DFC three-stage amplifier is designed and simulated in 0.5μm BCD process. Simulation results show that DMCNR-DFC three-stage amplifier achieves a dc gain of about 121.1dB and GBW of about 6.1MHz with 52º phase margin using a 5-V power supply voltage.


Keywords


dual-miller compensation with nulling-resistor, dual-feedforward compensation, three-stage amplifier

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DOI: http://doi.org/10.11591/ijeecs.v12.i8.pp6055-6062

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Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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