Active voltage balancing strategy of asymmetric stacked multilevel inverter

Abstract

Multilevel inverters (MLI) play an important role in AC applications and are undergoing continuous development in topology and control. In higher levels inverters, conventional MLIs have high components count which calls for modification of these topologies to obtain the same number of levels with fewer components to reduce cost and size. Balancing of the capacitors voltages is crucial for the operation of the MLI and it becomes more challenging in higher levels. This paper presents an active voltage balancing strategy for a reduced switch count five-leve topology which is the asymmetric stacked multilevel inverter (ASMLI). The ASMLI uses fewer components than the conventional MLIs when used in their five-levelconfiguration. The proposed active voltage balancing strategy uses simple measurements and logic to assure a balanced capacitors voltages during steady state and transients. The performance was examined and compared based on two modulation techniques with LCL filter and RL load using MATLAB/Simulink. The results show that the active voltage balancing strategy can trace all capacitors voltages to the reference value simultaneously with less than 1% voltage error, fast dynamic response, and an acceptable total harmonic distortion (THD) which allows the proposed setup to be an available option for medium voltage applications.