Parallel multi-layer selector S-Box based on lorenz chaotic system with FPGA implementation

Abstract

The substitution box (S-box) is the main block in the encryption system, which replaces the non-encrypted data by dynamic secure and hidden data. S-box can be designed based on complex nonlinear chaotic systems that presented in recent papers as a chaotic S-Box. The hardware implementation of these chaotic systems suffers from long processing time (low speed), and high-power consumption since it requires a large number of non-linear computational models. In this paper, we present a high-speed FPGA implementation of parallel multi-layer selector substitution boxes based on the lorenz chaotic system (PMLS S-Box). The proposed PMLS chaotic S-box is modeled using xilinx system generator (XSG) in 32 bits fixed-point format, and the architecture implemented into Xilinx Spartan-6 X6SLX45 board. The maximum frequency of the proposed PMLS chaotic S-box is 381.764MHz, with dissipates of 77 mwatt. Compared to other S-box chaotic systems, the proposed one achieves a higher frequency and lower power consumption. In addition, the proposed PMLS chaotic S-box is analyzed based on S-box standard tests such as; Bijectivity property, nonlinearity, strict avalanche criterion, differential probability, and bits independent criterion. The five different standard results for the proposed S-box indicate that PMLSC can effectively resist crypto-analysis attacks, and is suitable for secure communications.