A novel approach of multiplier design based on BCD decoder

Abstract

A novel approach of multiplier design is presented in this paper. The design idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A_5: A₀]_, using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems