Design of “ 32 ” Point Split Radix b ased Multipath Delay Commutator FFT Architecture for Low Power Applications

Abstract

FFT is used in Modern high speed signal processing application. In aforementioned technologies that tends to operate in various operational modes. To implement FFT obviously it not only needs to meet high throughput demand and also it needed to scalable cater selectable N point FFT. Our contribution to this paper is two-fold of our existing method, as proposes for the split radix using Multipath Delay Commutator (MDC) algorithm has the least complex design and less multiplications comparing to radix-2 algorithm. So that it can able to reduce power consumption and area than our existing work. The implementation of power efficient hardware of split radix FFT (SRFFT) is built up by pruning excessive computation. Leveraging this potential, a new architecture of a configurable SRFFT processor is first developed so that unnecessary computations, which yield zeros at the output, are pruned. Simulations show that maximum power saving of around 20% is achieved. The proposed algorithm consists of mixed radix butterflies, whose structure is more regular. It has the conjugate-pair version, which requires less memory.