Low-power high-speed FinFET DRAM array using sleep transistors

Abstract

Dynamic random-access memory (DRAM) is a fundamental memory technology widely employed in modern digital systems because of its high storage density and simple cell structure. However, conventional DRAM cells suffer from considerable power dissipation and propagation delay, which limit their suitability for high-speed and low-power applications. This paper presents three novel FinFET-based DRAM architectures incorporating sleep transistor techniques to reduce power consumption while improving operating speed. The proposed designs include a 2T-DRAM with sleep transistors and two configurations of 3T-DRAM with sleep transistors. The FinFET technology enhances switching performance and reduces propagation delay, whereas the sleep transistor technique effectively suppresses leakage, dynamic, and short-circuit power during memory operations. The proposed DRAM cells are designed and evaluated using the cadence virtuoso analog design environment. Simulation results demonstrate significant improvements over conventional DRAM architectures. The proposed 2T-DRAM achieves a 66% reduction in write delay, while the proposed 3T-DRAM achieves up to a 98% reduction in read delay. Furthermore, write power consumption is reduced by 56.8%, 63.02%, and 99.6% for the 2T, 3T-B, and 3T-C configurations, respectively. During read operations, power consumption is reduced by 99.8%, 99.5%, and 99.8%, respectively. These results demonstrate that the proposed FinFET DRAM architectures provide an effective solution for high-speed, low-power embedded memory applications.