A New Low-Costing QC-LDPC Decoder for FPGA

Zhao Han, M.R. Anjum

Abstract


Based on the Generalized Distributive Law and the features of FPGAs, this paper proposes a new strategy for implementation of Low-Costing QC-LDPC Decoder on FPGA platform. We get this new strategy from the Generalized Distributive Law, which is proposed to describe the belief propagation on graphs. And using this new strategy a low-costing (2560, 1024) LDPC decoder is implemented on a Xilinx Virtex-4 FPGA. Results show that this new strategy can make good use of the performance of LDPC codes, even though it needs less resource.


Keywords


LDPC Decoder, Low-Costing, Generalized Distributive Law, FPGA

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DOI: http://doi.org/10.11591/ijeecs.v12.i11.pp7721-7727

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Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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