A Design of Bang-Bang PLL in Low Jitter and Wide Pull-in Range

Xihong Chen, Qiang Liu, Denghua Hu


As bang-bang PLL (BBPLL) could resume clock data rapidly, its application in clock data recovery has become increasingly abroad. Aiming at the contrary demand of lower jitter and wider pull-in range of BBPLL, the issue puts forth a method to choose the most appropriate gain of digitally controlled oscillator (DCO) to settle. A judged and modified model has been added to the 2nd order traditional BBPLL, which modified the gain of DCO dynamically by step forward method. Meanwhile it proposes pull-in jitter function (PJF) to judge the modified results. Then it takes a gradual comparison means to search the max PJF. It could be concluded from the simulations that the algorithm of the issue could get a compromise DCO gain in view of BBPLL’s jitter and pull-in range.

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DOI: http://doi.org/10.11591/ijeecs.v12.i12.pp8212-8216


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The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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