Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip

Abstract

One promising approach for creating the chip-level connection of multiprocessing system on chip (MPSoC) is asynchronous logic. However, asynchronous systems are susceptible to errors. In this manuscript, the efficient fault-tolerant (FT) quasi-delay-insensitive (QDI) pipeline modules are designed using a delay-insensitive redundant check (DIRC) coding mechanism. The DIRC coding approach can tolerate single and multi-bit transient faults (TFs) in QDI-pipeline modules. The 4-phase 1-of-n coding approach incorporates DIRC-based QDI pipeline stages to strengthen the asynchronous links against TFs. The DIRC-based QDI pipeline stages are further used as asynchronous links in asynchronous network-on-chip ((NoC) for fault-free communication. The performance metrics like chip area, delay, and power parameters are evaluated in detail against different data widths for both basic unprotected and DIRC-based QDI pipeline modules.
The DIRC-based QDI-pipeline module with 1-of-4 code uses only <2% chip area with a delay of 7.4 ns and power of 117 mW on Artix-7 chip for data width 128. The code rate of the proposed work decreased by 33.33% for both 1-of-2 and 1-of-4 codes in DIRC-based QDI-pipeline modules.