Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

Subramanian Sumithra, Nagaiyanallur Lakshminarayanan Venkatara, Subramani Suresh Kumar, Ramaiah Purushothaman, Kathiresan Kokulavani, Velankanni Gowri


A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions.
The design of NoC is complex and the buffer section’s expensiveness creates problems while providing secured data service. Moreover, routers and links in NoC setups are liable to faults. This work introduces a minimal buffered router, and the faults in the network are optimized using moth flame optimized (MFO) fault-tolerant technique. The software named Xilinx ISE design suite 14.5 is employed for the minimum buffered router model.
The suggested scheme is operated with less area, low power (0.241 mW), and high speed (965.261 Megahertz (MHz)) when matched with previous works.


Fault tolerant technique; Minimum buffered; Moth flame optimization; Network-on-chip; Router

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The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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