Research on FPGA-based Programmable Logic Controllers’ Technology

Abstract

This paper introduces a scheme which implements the programmable logic controllers’ (PLCs) function based on FPGA. This scheme follows the IEC61131-3 standard, selects Ladder Diagram (LD) to write the PLC programs and selects VHDL as target language. Based on VS2005 platform, this scheme implements the construction of Ladder Diagram, compilation, simulation and other functions. This paper focuses on researching the construction method of Ladder Diagram, converting Ladder Diagram into Boolean equation and generating VHDL program by Boolean equivalence. The construction method of Ladder Diagram based on parallel-series hierarchical nested list and the implementing method of Boolean equivalence based on double-layer lists are proposed. Finally the correctness of the scheme is verified through an example.

 DOI: http://dx.doi.org/10.11591/telkomnika.v11i12.3701