D flip-flop design by adiabatic technique for low power applications

Abstract

Indigital circuits, energy reduction is the most important parameter in the design of handy and battery-operated devices. Flip- flop is an important component in any digital system. By improving the performance of flip-flop, complete system performance is better. This paper addresses the design of D flip-flop using direct current diode-based positive feedback adiabatic logic (DC-DB PFAL) at various frequencies at 45nm technology node. Further, the layout for the proposed design is also presented. The performance analysis is carried out for delay, power dissipation, power delay product and transistor count. Circuit simulation is done by using cadence virtuoso tool at 10 MHz and 100 MHz frequencies. The results show an improvement in power dissipation of 18% with less transistors count compared to exiting designs in the literature.