A High Performance Sigma-Delta ADC for Audio Decoder Chip

Abstract

This paper gives a high performance sigma delta Analog to Digital Converter (ADC) applied in computer audio decoder chip. In this design, a 3rd-order single-loop CIFF topology is chosen to achieve the high performance ADC. Its signal bandwidth is 20KHz, sampling frequency is 10.24MHz and oversampling ratio is 256. Local feedback coefficient is used to reduce quantization noise. The non-linear model of modulator is given and the stability is analyzed. It is got that when quantizer gain is bigger than 0.322 the system is stable. According to simulation, Signal to Noise Ratio (SNR) is 123.1dB and Effective Number of Bits (ENOB) is 20.15bits. When input level is bigger than -3dBFs, the modulator is overload and becomes unstable. Then the integrator, quantizer and feed forward summation in ADC circuit are designed.  Then the ADC is implemented in 0.6um CMOS process, and the test result shows that its performance is 99.28dB.

DOI: http://dx.doi.org/10.11591/telkomnika.v11i11.3498