Reconfigurable data encoding schemes for on-chip interconnect power reduction in deep submicron technology

Abstract

With technology scaling, size of both transistor and interconnects are reduced. Power dissipation due to dynamic switching is high in the interconnects. Suitable encoding schemes that reduces transition between data bits are used to minimize interconnect power dissipation. In this paper transition between data bits is minimized based on three novel data encoding schemes identifying the novel methods estimates bit transitions in a pair of data bits and performs half inversion or full inversion on one byte of data thus reducing the switching activity by 50%. The encoder and decoder for the three encoding schemes are modelled in verilog hardware description language (HDL) and implemented using application specefic integrates circuit (ASIC) flow targeting 32 nm. Technology over all power dissipation of encoding scheme is 1.04 μW in addition over head area of 210 cells with encoding delay of 340 ps. Encoder decoder register transfer logic (RTL) code is implemented and the total area required is 34980 units. The data encoding and decoding schemes are suitable for low power applications.