An efficient look up table based approximate adder for field programmable gate array

Hadise Ramezani, Majid Mohammadi, Amir Sabbagh Molahosseini

Abstract


The approximate computing is an alternative computing approach which can lead to high-performance implementation of audio and image processing as well as deep learning applications. However, most of the available approximate adders have been designed using application specific integrated circuits (ASICs), and they would not result in an efficient implementation on field programmable gate arrays (FPGAs). In this paper, we have designed a new approximate adder customized for efficient implementation on FPGAs, and then it has been used to build the Gaussian filter. The experimental results of the implementation of Gaussian filter based on the proposed approximate adder on a Virtex-7 FPGA, indicated that the resource utilization has decreased by 20-51%, and the designed filter delay based on the modified design methodology for building approximate adders for FPGA-based systems (MDeMAS) adder has improved 10-35%, due to the obtained output quality.

Keywords


Adders; Approximate computing; FPGA; Gaussian smoothing filter; LUTs;

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DOI: http://doi.org/10.11591/ijeecs.v25.i1.pp144-151

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