A Novel Unit Power Factor Rectifier Based on Three-phase Digital PLL

Xuegui Zhu, Zhihong Fu, Xiangfeng Su

Abstract


 

A novel three-phase phase-locked loop solution is proposed based on D-Q transformation aiming at the AC-DC rectifier with high efficiency and high power factor. The phase-locked loop is implemented digitally using the Xilinx blockset integrated with Matlab/Simulink. The three-phase digital phase-locked loop (TDPLL) is elaborately designed with the parameters defined in detail. The AC-DC converter (rectifier) model with the TDPLL is built and simulated in the high-speed VHS-ADC simulation platform from Canada. The simulation and test results show the TDPLL is locked right after the different three-phase voltage disturbances and very suitable for control of the rectifier with high parallelism through space vector pulse width modulation (SVPWM).

 

http://dx.doi.org/10.11591/telkomnika.v11i7.2850 

 


Keywords


digital phase locked loop (DPLL); field-programmable gate array (FPGA); rectifier; space vector pulse width modulation (SVPWM); high power factor

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Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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