Linearity improvement of differential CMOS low noise amplifier

Abstract

This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S₂₁ gain of 18.56 dB, noise figure (NF) of 1.85 dB, S₁₁ of −27.63 dB, S₂₂ of -34.33 dB, S₁₂ of −37.09 dB and IIP3 of -7.79 dBm.