FPGA implementation of color image encryption using a new chaotic map

Abstract

In this paper, an FPGA implementation of efficient image encryption algorithm using a chaotic map has been proposed. The proposed system consists of two phases image encryption technique. First phase consists of scrambling of pixel position and second phase consist of diffusion of bit value. In the first phase, original pixel values remain unchanged. In second phase, pixel values are modified. These modifications are done by using chaotic behavior of a recently developed chaotic map called Nahrain.  A color image encryption using Nahrain chaotic map is simulated in software via Matlab, Altera Quartus Prime 17.0 Lite EditionI and ModelSim software tools then implemented in hardware via Cyclone V GX Starter Kit FPGA platform. The results show the feasibility and effectiveness of the cryptosystem. As a typical application, the image encryption/decryption is used to demonstrate and verify the operation of the cryptosystem hardware. Complete analysis on robustness of the method is investigated. Correlation, Encryption time, Decryption time and key sensitivity show that the proposed crypto processor offers high security and reliable encryption speed for real-time image encryption and transmission.  To evaluate the performance, histogram, correlation, information entropy, number of pixel change rate (NPCR), and unified average changing intensity (UACI) measures are used for security analysis. The simulation results and security analysis have demonstrated that the proposed encryption system is robust and flexible. For example the amount of entropy obtained by the proposed algorithm is 7.9964, which is very close to its ideal amount: 8, and NPCR is 99.76 %, which is the excellent value to obtain. The hardware simulation results show that the number of pins that used of the proposed system reaches to 6% of total pins and Logic utilization (in ALMs) is 1%.