Regular Clocking Scheme based Design of Cost-efficient Comparator in QCA

Bibhash Sen, Jayanta Pal, Mojtaba Noorallahzadeh, Jyotirmoy Sil Sharma, Dhrubajyoti Bhowmik, Apu Kumar Saha

Abstract


Quantum-dot cellular automata (QCA) gains a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs have been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs still facing the challenges of cost efficiency, power dissipation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposes a novel cost effective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design is the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibits the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner is used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analysed.

Keywords


Comparator, Quantum-dot Cellular Automata, Cost AnRegular Clocking;QCADesigner;Power Analysis;QCAPro

References


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