Parallel Multi-Layer Selector S-Box based on Lorenz Chaotic System with FPGA Implementation

Mohamed Saber, Esam Hagras


In this paper, we present a high-speed FPGA implementation of Parallel Multi-Layer Selector Substitution Boxes based on Lorenz Chaotic System (PMLS S-Box). The proposed PMLS chaotic S-Box is modeled using Xilinx System Generator™ (XSG) in 32 bits fixed-point format, and the architecture implemented into Xilinx Spartan-6 X6SLX45
board. The maximum frequency of the proposed PMLS chaotic S-Box is 381.764 MHz
with dissipates of 77 mwatt. Compared to other S-BOX chaotic systems, the proposed one
achieves a higher frequency and lower power consumption. The proposed PMLS chaotic
S-Box is analyzed based on S Box slandered tests such as; Bijectivity property,
nonlinearity, strict avalanche criterion, differential probability and bits independent
criterion. The five different standard results for the proposed S-Box indicates that PMLSC
can effectivity resist to cryptanalysis attacks, and is suitable for secure communications


chaotic systems, s-box , fpga


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