Comparative Analysis of Time and Physical Redundancy Techniques for Fault Detection

Namita Arya, Amit Prakash Singh

Abstract


The integration level in today’s world is continuously increasing in VLSI chips. VLSI circuit verification is a major challenge in these days. Integration capacity of VLSI circuits mimics the testing complexity of circuits. There is a significant chunk of the testing cost with respect to the whole fabrication prices. Hence it is important to cut down the verification cost. Time required during testing is a main factor for the cost of a chip. This time is directly proportional to the number of testing in the circuitry. So the test set should be very small. There is one way to generate a small test set is to compact a large test set parameters. The main drawback of the compaction results on the quality of the original test set. This aspect of compaction has motivated the work present here with some methods of fault detection and avoidance techniques via redundancy logic as Time redundancy and physical redundancy.


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DOI: http://doi.org/10.11591/ijeecs.v6.i1.pp66-71

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