Design of ECC Controller and its Validation Based on FPGA

Abstract

ECC is an advanced technology for memory error detection and correction, which is used to support high reliability of computers. It is widely used in sever memory while it can detect 2-bit error and correct 1-bit error. This paper introduces the ECC algorithm, then discusses the more general correction coding mathematics, realizing it by programming with VHDL. After finishing these parts, a debug experiment is executed on the Altera Stratix IV family FPGA. Finally, the paper analyzes the simulation results and gives some suggestions for improving the performance of ECC controllers.