Mathematical model enhancing flash memory reliability through DFT-driven error correction coding

Poornima Huchegowda Sukanya, Nagaraju Chowdaiah


Flash memory, ubiquitous in diverse electronic devices, confronts persistent challenges stemming from inherent errors that jeopardize data integrity. This research situates itself at the intersection of these challenges and advancements, proposing an inventive error correction coding framework that harnesses the unique capabilities of analysis with a hybrid error control coding (HECC) approach. In the proposed work, a mathematical model aimed at enhancing the flash memory by identifying the error pattern within the pages using the discrete fourier transform (DFT). By incorporating distinctive DFT mathematical properties, the proposed technique intends to improve flash memory error correction beyond traditional methods. The flash storage defect detection and rectification results with hybrid error correction coding achieved bit error rate (BER) of 4.3e-6, latency 14.1, mean 15.1 and standard deviation 1.0. Error correction efficiency 98% and storage overhead 10%. With this approach results are significantly improving the error correction efficiency, reduce storage overhead and enhanced adaptability to diverse error patterns.


Bit error rate; Discrete fourier transform; Error control coding; Flash memory; Reliability enhancing

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Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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