Analysis of FinFET based SRAM cells with improved performance parameters

Abstract

To resist the advanced process variation and enable ultra-low power operation, static random-access memory (SRAM) undergoes an expansion stage. The most common type of memory is SRAM, which occupy more than 60% of the chip area. All memories have occupied more than 80% of the circuit area in that day’s micro devices, and this trend is expected to continue. This paper develops into the deployment of SRAM using FinFET technology for implementation, with a primary objective of mitigating critical memory parameters, including parameters named as power dissipation, data retention and noise voltage. In this article, multiple simulations are carried out among conventional SRAM cells and FinFET based SRAM cells (6T, 7T, and 8T) utilizing the Cadence Virtuoso tool with a 45nm technology node. In modern era, FinFET is gaining increased preference over CMOS for high controllability of short-channel effects and flexible adjustment of threshold voltage (Vth) through the presence of a double gate. The thinner width of FinFET (Wfin) shows less degradation in performance in compared to thicker width of FET. To improve the circuit performance, the key factors like area, power and delay should be reduced. In the proposed SRAM cell using FinFET, power dissipation is lowered by 17% data retention voltage is reduced by 7% and noise voltage abridged up to 35% as compared to conventional SRAM cell.