ADKNN fostered BIST with Namib Beetle optimization algorithm espoused BISR for SoC-based devices

Suleman Alnatheer, Mohammed Altaf Ahmed

Abstract


Redundancy analysis is a widely used method in fault-tolerant memory systems, and it is essential for large-size memories. In current security operations centers (SoCs), memory occupies most of the chip space. To correct these memories using a conventional external equipment test approach is more difficult. To overcome this issue, memory creators utilize redundancy mechanism for substituting the columns and rows along with a spare one to increase output of the memories. In this study, a built-in-self-test (BIST) to test memories and built-in-self-repair (BISR) mechanism to repair the faulty cells for any recent SoC devices is proposed. The BIST, based on adaptive activation functions with a deep Kronecker neural network (ADKNN), not only detects the defect but also determines the kind of defect. The BISR block uses the Namib Beetle optimization algorithm (NBOA) to fix the mistakes in the memory under test (MUT). The study attempts to determine how the characteristics of SoC-based devices change in the real world and then contributes to the suggested controller blocks. Performance metrics such as slice register, region, delay, maximum operating frequency, power consumption, minimum clock period, and access time evaluate performance. Comparing the proposed ADKNN-NBOA-BIST-BISR scheme to existing BIST, BISR, and BISD-based methods reveals its significant performance.

Keywords


ADKNN; BIST and BISR; Built-in redundancy analysis; Memory under test; NBOA; System-on-chips

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DOI: http://doi.org/10.11591/ijeecs.v35.i1.pp90-101

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The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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