Parameterized SDRAM-based content-addressable memory on field programmable gate array

Abstract

Contents-addressable memory (CAM) is a special memory that searches the input data with the entire pre-loaded database and generates corresponding address information. CAMs are advancing to be a core technology in computer networking systems. As field programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate CAM on FPGA is increasing. FPGA-based CAMs are divided into three categories of implementation: register-based, block RAM (BRAM)-based, and distributed RAM-based CAM. However, they come with a cost of excessive resource usage. Besides, the collision ratio is high in FPGA-based CAMs, leading to data loss and failure to produce accurate addresses. Synchronous dynamic random-access memory (SDRAM)-based CAMs, benefiting from the features of high density and low price of SDRAM, solve the limitations of FPGA’s on-chip resources. This paper proposes a data collision CAM hardware implementation using modern FPGA’s off-chip SDRAM for data storage. The hardware architecture is customized for massive lookup tables and resource-saving. Furthermore, the architecture is parameterized, which is better for integration. The synthesis results and comparisons show significant advancement compared to other FPGA-based CAM implementations by total reduction of on-chip RAM. The novel architecture shows remarkable improvement in the memory depth and width with the capacity of 128 Mbyte lookup table.