Efficient hardware implementation for lightweight Loong algorithm using FPGA

Marwa Subhi Ibrahim, Yasir Amer Abbas, Mudhafar Hussein Ali

Abstract


Recently low-resource devices such as radio frequency identification (RFID), internet of things (IoT), and wireless sensor networks (WSN) using lightweight cryptography (LWC) to protect devices. Created or design low-resource devices with a lightweight cryptographic technique should take into account important factors such as the battery life and the amount of data to be processed. This paper provides a new hardware designed for Loong lightweight cryptographic algorithm that takes into account the previously described constraints. The new hardware architecture for Loong algorithm with resource sharing to reduce system designed. The proposed approach is implemented using ISE Xilinx V14.7 using Virtex 4 field programmable gate array (FPGA) platform. The synthesis analysis for ISE showed the throughput of 851.264 Mbps with efficiency of 2.282 Mbps/slice, and a power consumption of 0.193 Watt. The implementation designed show the all-algorithms size consists of 373 slices, and the maximum possible operating frequency is 212.816 MHz. To the best of our knowledge, this is the first time that Loong algorithm has been implemented on FPGA using very high-speed integrated circuit hardware description language (VHDL).

Keywords


Field programmable gate array; Hardware architecture; Lightweight; Loong; VHDL

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DOI: http://doi.org/10.11591/ijeecs.v30.i1.pp451-459

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