Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair

Gobinda Prasad Acharya, Muddapu Asha Rani, Ganjikunta Ganesh Kumar, Lavanya Poluboyina


The technology shrinkage and the increased demand for high storage memory devices in today’s system on-chips (SoCs) has been the challenges to the designers not only in the design cycle but also to the test engineers in testing these memory devices against the permanent faults, intermittent and soft errors. Around 90% of the chip area in today’s SoCs is being occupied by the embedded memories, and the cost for testing these memory devices contributes a major factor in the overall cost and the time to market. This paperproposes a strategy to develop a word-oriented March SS algorithm-basedmemory built-in self-test (MBIST), which is then applied for memory built-in self-test and repair (MBISTR) strategy. The implementation details for 1 KB of single-port static random-access memory (SRAM) depict that the modified March-SS algorithm based MBISTR-enabled SRAM facilitates self-test and self-repair of embedded memories with a marginal hardware overhead (<1%) in terms of look up tables and slice registers when compared to that of standard SRAM.


Built-in self-test; Fault-map unit; March SS algorithm; Memory built-in self-repair; SRAM; System-on-chip

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