Low power residue number system using lookup table decomposition and finite state machine based post computation

Balaji Morasa, Padmaja Nimmagadda

Abstract


In this paper, memory optimization and architectural level modifications are introduced for realizing the low power residue number system (RNS) with improved flexibility for electroencephalograph (EEG) signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance finite impulse response (FIR) filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed lookup table (LUT) model which can produce the results without using any post accumulation process. The reverse conversion block is modified with an appropriate functional unit to accommodate FIR convolution results. The proposed approach is established to develop and execute pre-calculated inverters for various module sets. Therefore, the proposed LUT-decomposition with RNS multiplication-based post-accumulation technology provides a high-performance FIR filter architecture that allows different frequency response configuration elements. Experimental results shows the superior performance of decomposing LUT-based direct reverse conversion over other existing reverse conversion techniques adopted for energy-efficient RNS FIR implementations. When compared with the conventional RNS FIR design with the proposed FSM based decomposed RNS FIR, the logic elements (LEs) were reduced by 4.57%, the frequency component is increased by 31.79%, number of LUTs is reduced by 42.85%, and the power dissipation was reduced by 13.83%.

Keywords


Electroencephalograph; Finite impulse response; FPGA; MODELSIM; Residue number system

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DOI: http://doi.org/10.11591/ijeecs.v26.i1.pp127-134

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