Low Cost Quasi Binary Weighting Addition Log-SPA LDPC Decoders

Abstract

This paper proposes a new addition method, which can be applied to reduce the hardware cost of LDPC decoders using log-SPA, which traditionally has the best lowest bit error rate (BER) but the highest hardware requirement. The proposed quasi-binary weighting addition can be simply implemented by OR gates. With auxiliary pseudo-carry circuit, the BER performance can reach a fair level. In the log-SPA message-passing path, numeric transform reduction architecture is proposed for further hardware reduction. Synthesized and numerical results show that the new proposed architecture achieved an up to 32% and 18% total hardware reduction, compared with traditional log-SPA decoders, and the simplest sign-min architecture, respectively, with fair BER performance.

DOI: http://dx.doi.org/10.11591/telkomnika.v11i5.2505