A compact FPGA-based montgomery modular multiplier

Ahmed A. H. Abd-elkader, Mostafa Rashdan, El-Sayed A. M. Hasaneen, Hesham F. A. Hamed


This paper presents the FPGA-based implementation of compact montgomery modular multiplier (MMM). MMM serves as a building block commonly required in security protocols relying on public key encryption.  The proposed design is intended for hardware applications of lightweight cryptographic modules that is utilized for the system on chip (SoC) and internet of things (IoT) devices. The proposed design is a modification in the structure of MMM without any multiplication or subtraction processes. The main target of the new modification is enhancing the performance and reducing the area of the MMM hardware module. The operands and internal variables of the proposed hardware circuit is optimized to be bounded to the smallest efficient size to minimize the area and the critical path delay.   The proposed design was coded in VHDL, implemented in the Virtex-6 FPGA, and its performance was analyzed utilizing XILINX ISE tools. Our design occupies the smallest area comparing with other implementations on the same FPGA type. The proposed design saves in a range between 60.0 and 99.0% of the resources compared with other relevant designs.


FPGA; Lightweight cryptography; LUT; Modular multiplier; Virtex-6

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DOI: http://doi.org/10.11591/ijeecs.v21.i2.pp735-743


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The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

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