Hardware design of a scalable and fast 2-D hadamard transform for HEVC video encoder

Heh Whit Ney, Ab Al-Hadi Ab Rahman, Ainy Haziyah Awab, Mohd Shahrizal Rusli, Usman Ullah Sheikh, Goh Kam Meng


This paper presents the hardware design of a 2-dimensional Hadamard transform used the in the rate distortion optimization module in state-of-the-art HEVC video encoder. The transform is mainly used to quickly determine optimum block size for encoding part of a video frame. The proposed design is both scalable and fast by 1) implementing a unified architecture for sizes 4x4 to 32x32, and 2) pipelining and feed through control that allows high performance for all block sizes. The design starts with high-level algorithmic loop unrolling optimization to determine suitable level of parallelism. Based on this, a suitable hardware architecture is devised using transpose memory buffer as pipeline memory for maximum performance. The design is synthesized and implemented on Xilinx Kintex Ultrascale FPGA. Results indicate variable performance obtained for different block sizes and higher operating frequency compared to a similar work in literature. The proposed design can be used as a hardware accelerator to speed up the rate distortion optimization operation in HEVC video encoders.


RTL, Hadamard transform, SATD, HEVC, FPGA

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DOI: http://doi.org/10.11591/ijeecs.v15.i3.pp1401-1410


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