Low power circuit design using NCL based asynchronous method

Toi Le Thanh, Lac Truong Tri, Trang Hoang

Abstract


Power consumption of the electronic devices becomes one of the major concerns in synchronous circuits and asynchronous circuits, especially Null Convention Logic (NCL) is gaining more attention. The NCL based circuit design methodology eliminates the problems related to noise, clock tree, electromagnetic interference and also reduces significant power consumption. In this paper, we would like to demonstrate the advantage of low power consumption of the NCL based asynchronous circuit design on a large design scale, thus we used the AES (Advanced Encryption Standard) encryption design as an illustrative example. In addition, we also proposed two pipelined AES encryption models using the synchronous circuit design technique and the asynchronous circuit design technique based on NCL. Besides, these two models were realized by using VCS tool to simulate and Design Compiler tool to synthesize parameters in power consumption, processing speed and area. The synthesis results of these two models indicated that power consumption of the NCL based asynchronous AES encryption model had a decrease of 71 % compared with the synchronous AES encryption model. Moreover, we show the outstanding advantage of the power consumption of the NCL based asynchronous design model (a decrease of 91.12% and 93,23%) compared to the synchronous design model using clock gating technique and without using clock gating technique respectively. This work could be one of the foundations to help the IC designers choose the appropriate design method in low power applications.

Keywords


Advanced encryption standard (AES); Asynchronous method; Low power; Null convention logic (NCL); Synchronous method



DOI: http://doi.org/10.11591/ijeecs.v22.i3.pp%25p

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