New voltage and temperature scalable gate delay model applied to a 14nm technology

Kenza Charafeddine, Faissal Ouardi

Abstract


The following work shows an innovative approach to model the timing of standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work, characterization of cells of a standard cell library is done in an hour whereas it is done in 650 hours with the classical method. Also, a method for validating and verification of the precision of the modelled data is resented by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.


Keywords


Characterization; Liberty file; Library; Scaling; Standard cell; Temperature; Timing; Voltage

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DOI: http://doi.org/10.11591/ijeecs.v20.i3.pp1210-1220

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