Design of 130nm RFCMOS differential low noise amplifier

Maizan Muhamad, Hanim Hussin, Norhayati Soin

Abstract


In this paper, an inductively degenerated CMOS differential low noise amplifier circuit topology is presented. This low noise amplifier is intended to be used for wireless LAN application. The differential low noise amplifier proposed provide high gain, low noise and large superior out of band IIP3. The LNA is designed in 130 nm CMOS technology. Simulated results of gain and NF at 2.4GHz are 20.46 dB and 2.59 dB, respectively. While the simulated S11 and S22 are −11.18 dB and −9.49 dB, respectively. The IIP3 is −9.05 dBm. The LNA consumes 3.4 mW power from 1.2V supply. 

Keywords


CMOS; Differential; Low noise amplifier (LNA); Noise figure (NF)



DOI: http://doi.org/10.11591/ijeecs.v19.i1.pp%25p
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