Design and implementation of fast floating point units for FPGAs

Mohammed Falih Hassan, Karime Farhood Hussein, Bahaa Al-Musawi

Abstract


Due to growth in demand for high-performance applications that require high numerical stability and accuracy, the need for floating-point FPGA has been increased. In this work, an open-source and efficient floating-point unit is implemented on a standard Xilinx Sparton-6 FPGA platform. The proposed design is described in a hierarchal way starting from functional block descriptions toward modules level design. Our implementation used minimal resources available on the targeting FPGA board, tested on Sparton-6 FPGA platform and verified on ModelSim. The open-source framework can be embedded or customized for low-cost FPGA devices that do not offer floating-point units.


Keywords


IEEE floating-point; FPGA architecture; Floating-point unit (FPU); Embedded block.

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DOI: http://doi.org/10.11591/ijeecs.v19.i3.pp1480-1489

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