DES encryption and decryption algorithm implementation based on FPGA

Subhi R. M. Zeebaree

Abstract


Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept.  The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

Keywords


Cryptography; DES algorithm;FPGAs; VHDL; Block cipher

Full Text:

PDF


DOI: http://doi.org/10.11591/ijeecs.v18.i2.pp774-781
Total views : 190 times

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

shopify stats IJEECS visitor statistics