A Simplified PWM Technique for Reduced Switch Count Multilevel Inverter

Received Sep 19, 2017 Revised Dec 30, 2017 Accepted Jan 17, 2018 Penetration of multilevel inverters (MLI) in to high power and medium voltage application has been increasing because of its advantages. A conventional two level inverter has high harmonic distortion which gives poor power quality. Lot of topologies has been developed to overcome the drawbacks of two level inverter. These topologies include more number of switching devices which increases the design complexity and cost. The optimum design of inverter requires less number of switches with better quality in waveform. In this paper, a symmetrical five level and seven level inverter configuration with simplified pulse width modulation technique is proposed. This proposed inverter requires less switches, less protection circuits along with low cost and size. The analysis of the inverter circuits is done by using Matlab/Simulink software. The synthesized staircase wave form is shown and total harmonic distortion (THD) is also measured.


INTRODUCTION
In recent years, the industries have started to operate at higher power rating machines. And for some medium voltage drives and applications, they need medium voltage and high power level. For this purpose, multilevel inverter [1]- [3] concept has been developed for high power and medium voltage applications. These inverters are not only used for high power applications, but also used for interfacing the renewable energy sources (RES) [4]- [6] to the utility grid. The renewable energy sources like solar, wind and fuel cell could be easily connected to the grid using multilevel inverters. The multilevel inverter concept has been introduced since 1975. It has started with a three level inverter and consequently lot of inverter topologies has been introduced.
However, the major objective of the multilevel inverter is to get high power using power semiconductor switches with number of low voltage dc sources. The characteristics of less total harmonic distortion (THD) [7][8], reduced dv/dt and low common mode voltage are the reasons for getting popularity for the multi-level inverters in medium voltage and high power applications. The advantages of multilevel inverter are given below. a. Reduces the electromagnetic compatibility problems because of low dv/dt stress and less harmonic distortion. b. The common mode voltage of a multilevel inverter is small. Therefore, if a multilevel inverter is connected to drive the stresson the bearing will be reduced. c. The current drawn by the multilevel inverter has low distortion. d. Multilevel inverters can able to operate at fundamental as well as high switching frequency.
However, more number of switching devices in the inverter causes to decrease the efficiency and reliability of the drive [9]- [10]. Therefore, it is necessary to improve the reliability and efficiency by reducing the number of switches. In this paper, a reduced switch count multilevel inverter for five and seven level is proposed. A simplified pulse width modulation technique is implemented for control strategy [11]. A five level inverter is proposed with five switches and a 7 level inverter is proposed with six switches. These circuits are implemented using Matlab/Simulink software. The total harmonic distortion for voltage wave form is measured by fast Fourier transform analysis.

FIVE SWITCH FIVE LEVEL INVERTER
The proposed 5 switch five level multilevel inverter is shown in figure 1. This topology consists of four switches of IGBT and one ideal switch. The source voltage is divided in to two equal parts as V dc /2each. The configuration of the circuit with R load is shown.
The required five level output voltage levels 0, V dc /2, V dc , -V dc/2 and -V dc are obtained by operating these five switches in proportional manner. The diagrams for each level are illustrated in following figures.

Level -0
To get zero voltage level, the switches S2 and S4 should be turned on. The load becomes short circuit and the voltage across it is zero. The operational diagram is shown in Figure 2.

Level -V dc/2
The voltage level of Vdc/2 is produced by switching ON the switches S2 and S5.In this case only bottom source is connected to the load and the voltage V dc/2 appears across the load. The operational diagram is shown in figure 3.
Level -V dc By switching ON switches S1 and S2 we can get the voltage level of V dc . In this case both the voltage sources appear across the load. The operational diagram is shown in Figure 4.

Level --V dc/2
The -V dc/2 voltage level is obtained by closing the switches S3 and S5. In this case the upper voltage source is connected to the load. The operational diagram is shown in Figure 5.

Level --V dc
The voltage level -V dc could be obtained by operating the switches S3 and s4. Both the voltage sources are connected to load with negative polarity. The operational diagram is shown in Figure 6.
The Table 1 shows the switching pattern for five switch five level inverter.

SIX SWITCH SEVEN LEVEL INVERTER
The proposed 6 switch seven level multilevel inverter is shown in Figure 7. This topology consists of four switches of IGBT and two ideal switches. The source voltage is divided in to three equal parts as Vdc/3each. The configuration of the circuit with R load is shown.   Figure 10. Operational diagram for level 2V dc/3 Figure 11 Operational diagram for level V dc Figure 12 Operational diagram for level -V dc/3 Figure 13 Operational diagram for level -2V dc/3

Level -0
To get zero voltage level, the switches S2 and S4 should be turned on. The load becomes short circuit and the voltage across it is zero. The operational diagram is shown in Figure 8.

Level -V dc/3
The voltage level of Vdc/3 is produced by switching ON the switches S2 and S6.In this case only bottom source is connected to the load and the voltage V dc/3 appears across the load. The operational diagram is shown in Figure 9.

Level -2V dc/3
The voltage level of 2Vdc/3 is produced by switching ON the switches S2 and S5.In this case bottom two sources are connected to the load and the voltage 2V dc/3 appears across the load. The operational diagram is shown in Figure 10.

Level -V dc
By switching ON switches S1 and S2 we can get the voltage level of V dc . In this case all the voltage sources appear across the load. The operational diagram is shown in Figure 11.

Level --V dc/3
The voltage level of -V dc/3 is produced by switching ON the switches S3 and S5.In this case only upper source is connected to the load and the voltage -V dc/3 appears across the load. The operational diagram is shown in Figure 12.

Level --2V dc/3
The voltage level of 2V dc/3 is produced by switching ON the switches S3 and S6.In this case top two sources are connected to the load and the voltage -2V dc/3 appears across the load. The operational diagram is shown in Figure 13. Level --V dc By switching ON switches S3 and S4 we can get the voltage level of -V dc . In this case all the voltage sources appear across the load. The operational diagram is shown in Figure 14.

SIMPLIFIED PWM TECHNIQUE 4.1. For Five Switch Five Level
In multilevel inverters the output voltage is controlled by using different modulation strategies. In PWM control, there are three techniques like fundamental switching frequency PWM, PWM technique based on carrier and space vector PWM technique. Among these, the carrier based PWM technique is frequently used because; it has less complexity even when output voltage levels are more. In this paper, a multi-carrier based SPWM (sinusoidal pulse width modulation) technique has been implemented. It contains a reference signal which is compared with the two high frequency carrier signals to generate switching states A, B and C (Figure 15). The two carriers have a small difference in its magnitude which are disposed vertically. By combining these switching states, the gating pulses are generated for the switches using following logical notation.

For Six Switch Seven Level
In this control three carrier waveforms are used to generate the four switching states. The logical combination of four switching states A, B, C and D gives us the pulses for switches S1 through S6. The PWM technique and switching logic is given.
By combining these switching states, the gating pulses are generated for the switches using following logical notation.

Case 2: RL-Load
The output voltage waveform is shown in Figure 21.   The total harmonic distortion for voltage wave form is given in figure 25 and the THD measured is 26.87%.

Six Switch Seven Level Inverter Case 1: R-load
The output voltage of six switch seven level is shown in Figure 26.  Figure 26. Output voltage Figure 27 shows the output current.

CONCLUSION
In this paper, the five switch five level and a six switch seven level multilevel inverter is proposed. A simplified pulse width modulation technique also has been implemented for proposed inverters. Based on the PWM wave forms a digital switching logic has been developed and implemented to the control logic. The five level and seven level inverters are analyzed with R and RL load and the results are presented. The total harmonic distortion is also measure for both the levels. The THD for five level is 26.87% and for seven level is 18.18%.