Savugathali, Salahuddin, Univeristy Malaysia Perlis, Malaysia

• Vol 14, No 2: May 2019 - Special_Invitation
  Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques
  Abstract  PDF
• Vol 14, No 2: May 2019 - Special_Invitation
  Manual clock distribution technique in partitioning stage for multi-FPGA prototyping
  Abstract  PDF

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