Efficient Phase Recovery System

Mohamed Saber

Abstract


An efficient, stable and reliable system to detect the unknown phase of the input sinusoidal signal is presented. The proposed design is a feedback loop consists of subtractor, peak detector and direct digital synthesizer (DDS). DDS generates a sinusoidal signal with the same frequency of input signal and with initial zero phase. An error signal is the output of subtracor after subtracting DDS signal from input signal. The peak of amplitude of error signal has a mathematical relation to the phase difference between the two input signals. Peak detector is used to extract the phase difference from error signal and passes the result to DDS to control the generated phase. The loop continues until the generated phase of DDS is the same as the input unknown phase. The proposed phase estimator has been implemented using a field programmable gate array (FPGA), consumed less power about 330 mW, and worked at 200 MHz clock.


Keywords


Phase recovery, Direct digital frequency synthesizer, FPGA, PLL

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DOI: http://doi.org/10.11591/ijeecs.v5.i1.pp123-129

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