Efficient H.264 Decoder Architecture using External Memory and Pipelining

G.R. Poornima, S C Prasanna Kumar

Abstract


A H.264 standard is one of the most popular coding standard with significant improvement in video broadcasting and streaming application. However it’s significant in compression but needs huge calculation and complex algorithm for providing better image quality and compression rate. In H.264 coding technique, designing of decoder is a key factor for efficient coding. In this paper we are designing a decoder using a complex input. We ensured several improvement like looping arrangement, buffer upgradation, buffer supplement, memory reusability and pipelining architecture. We have modified the memory structure also. Our designed decoder achieves a better frame decoding efficiency against state-of-art methods. The proposed approach also provides good area optimization with a maximum frequency of 355 MHz.


Keywords


H.264 decoder; pipelining architecture; Memory reusability;Luma/Chroma

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DOI: http://doi.org/10.11591/ijeecs.v12.i3.pp995-1002

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