A Low Quiescent Current Fast Settling Capacitor-less Low Drop Out Regulator Employing Multiple Loops

Suresh Alapati, Patri Sreehari Rao

Abstract


This paper presents a fast transient and low noise capacitor-less LDO using multiple loops. The proposed LDO exploits adaptive biasing, bulk modulation and a fast reacting control loop for achieving high performance striking reasonable tradeoffs among quiescent current, transient response and stability. The proposed LDO offers a load regulation of 0.095µV/mA while consuming quiescent current of 16 µA. It exhibits a load transient of 134.23mV with a settling time of 240.8ns against 0 to 100mA load variation with 40pF output capacitor. It exhibits an integrated noise of 31.027 pV2 /Hz at 10 Hz for a maximum load current of 100mA. The proposed LDO is designed using 0.18-µm 1P6 CMOS process.


Keywords


Dropout voltage; Adaptive biasing; Bulk modulation; Telescopic amplifier; Voltage regulator

Full Text:

PDF


DOI: http://doi.org/10.11591/ijeecs.v10.i3.pp1070-1079

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS)
p-ISSN: 2502-4752, e-ISSN: 2502-4760
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).

shopify stats IJEECS visitor statistics